GameCube Hardware Registers

Based on Titanik’s Information

Last Updated: September 24, 2003

Compiled by: Azimer

Note: If you have any new information or bugfixes, PLEASE contact me on IRC.

Note 2: This document may be difficult to read and inconsistently formatted, please bare with me.  Information is the top priority and format

is the second.  These problems will be resolved as information is more concrete.  I do plan on adding detailed documents later for each register set.

CC000000

CC001000

CC002000  R/W  16 bit    Vertical Timing Register *Untested*

                                        00AA AAAA AAAA EEEE

                                        A = Active Video (In HalfLines)

                                        E = Equalization pulse in half lines

CC002002  R/W  16 bit    Display Configuration Register

                                        0000 00PP LLTT DIRE

                                        PP = Current Video Format

                                            0 - NTSC 1 - PAL 2 - MPAL 3 - Debug

                                        LL = Enables Display Latch 0 *In Progress*

                                            0 - Off 1 - On for 1 field

                                            2 - On for 2 fields 3 - Always On

                                        TT = Enables Display Latch 1 *In Progress*

                                            0 - Off 1 - On for 1 field

                                            2 - On for 2 fields 3 - Always On

                                        D = Selects 3D Display Mode

                                        I = Interlace Selector *In Progress*

                                            0 = Interlaced, 1 = Non-Interlaced

                                        R = Reset - Clears all data requests

                                            and puts VI into its idle state.

                                        E = Enable - Enables video timing

                                            generation and data request.

CC002004  R/W  32 bit   Horizontal Timing 0 Register

                                        0SSS SSSS 0EEE EEEE 0000 000W WWWW WWWW

                                        S = Horizontal Sync Start to Color Burst End

                                        E = Horizontal Sync Start to Color Burst Start

                                        W = Halfline Width (W*16 = Width (720))

CC002008  R/W  32 bit   Horizontal Timing 1 Register

                                        0000 0SSS SSSS SSSE EEEE EEEE EWWW WWWW

                                        S = Half line to horizontal blanking end

                                        E = Horizontal Sync Start to horizontal blank end

                                        W = Horizontal Sync Width

                                            Setting bit 0 seems to blackout the screen.

                                            Similar to ViBlack??

CC00200C  R/W  32 bit    Odd Field Vertical Timing Register *Untested*

CC002010  R/W  32 bit    Even Field Vertical Timing Register *Untested*

CC002014  R/W  32 bit    Odd Field Burst Blanking Interval Register *Untested*

CC002018  R/W  32 bit    Even Field Burst Blanking Intverval Register *Untested*

CC00201C  R/W  32 bit    Top Field Base Register (L)

                                        000? XXXX FFFF FFFF FFFF FFF0 0000

                                        X = Horizontal Offset of the left-most pixel

                                            within the first word of the fetched

                                            picture.

                                        F = External Memory Address of frame buffer

CC002020  R/W  32 bit    Top Field Base Register (R) (Only valid in 3D Mode)

                                        0000 0000 FFFF FFFF FFFF FFF0 0000

                                        F = External Memory Address of frame buffer

CC002024  R/W  32 bit    Bottom Field Base Register (L)

                                        0000 0000 FFFF FFFF FFFF FFF0 0000

                                        F = External Memory Address of frame buffer

CC002028  R/W  32 bit    Bottom Field Base Register (R) (Only valid in 3D Mode)

                                        0000 0000 FFFF FFFF FFFF FFF0 0000

                                        F = External Memory Address of frame buffer

CC00202C  R    32 bit    Display Position Register

                                        0000 00VV VVVV VVVV 0000 00HH HHHH HHHH

CC002030  R/W  32 bit    Display Interrupt 0

                                        I00E 00VV VVVV VVVV 0000 00HH HHHH HHHH

                                        I = Interrupt Status (1=Active) (Write to clear)

                                        E = Interrupt Enable Bit

                                        V = Vertical Position

                                        H = Horizontal Position

CC002034  R/W  32 bit    Display Interrupt 1

                                        Refer to Display Interrupt 0

CC002038  R/W  32 bit    Display Interrupt 2

                                        Refer to Display Interrupt 0

CC00203C  R/W  32 bit    Display Interrupt 3

                                        Refer to Display Interrupt 0

CC002040  W    16 bit?   Unknown

CC002042  W    16 bit?   Unknown

CC002044  W    16 bit?   Unknown

CC002046  W    16 bit?   Unknown

CC002048  R/W  32 bit    Scaling Register

                                        WWWW WWWW ???? ???? 000E 000V VVVV VVVV

                                        W = Frame Buffer Width (divided by 16)

                                        E = Enable Horizontal Scaling

                                        V = U1.8 Scaler Value (0x160 Works for 320)

CC00204C thru CC002067  Skipped for now (AA stuff)

CC00206C  R/W  16 bit    VI Clock Select Register

                                        0000 0000 0000 000S

                                        S = 0 - 27 Mhz video clk

                                            1 - 54 Mhz video clk (Progressive Mode)

CC002070  R/W  16 bit   Holds 0x280, but has no effect on change (Possibly for Progressive)

                        I can not test this theory without a TV that supports Progressive

PI (Processor Interface) : *This is my current work in progress…  most information is misleading*

CC003000  R    32 bit    Cause Register

                                        xxxx xxxx xxxx xxxx xxHG CPTV MDAE SKWR

                                        R = Error

                                        W = Reset Switch Interrupt

                                        K = DI Interrupt

                                        S = SI Interrupt

                                        E = EXI Interrupt
                                        A = AI Interrupt

                                        D = DSP Interrupt

                                        M = MI Interrupt

                                        V = VI Interrupt

                                        T = Pixel Engine Token

                                        P = Pixel Engine Finish

                                        C = CP Interrupt

                                        G = Debug Interrupt

                                        H = HSP ??

CC003004  R/W  32 bit    Interrupt Mask (See CC003000 for bits)

CC003010  ?/?  32 bit    FIFO End??

CC003014  ?/?  32 bit    FIFO Write Pointer??

CC00301C  ?/?

CC003024  R/W  32 bit?   Reset? – Writing anything here seems to cause a complete reset.

MI (Memory Interface) :

CC004010  ?/?  16 bit    ??? (just set it to 0xFF)

CC00401C  ?/?  16 bit    MI Mask Register??

CC00401E  ?/?  16 bit    MI Cause Register??

CC004020  ?/?  16 bit    ??? (just set it to zero)

CC004022  ?/?  16 bit    ???

CC004024  ?/?  16 bit    ???

CC004028  ?/?  16 bit    ??? – 2 after init if RAM is 24MB

AI (Audio Interface) :

CC005000  ?/?  16 bit?   DSP Status

CC005002  ?/?  16 bit?   DSP (2) \

CC005004  ?/?  16 bit?   DSP (3)  -- Communication with DSP?

CC005006  ?/?  16 bit?   DSP (4) /

CC00500A  ?/W  16 bit    AI Control Register          |???? ???D DRRA A??S|

                                                     High D = DSP Int Mask, Low D = DSP Int Bit

High R = ARAM Int Mask, Low R = DSP Int Bit

High A = AI Int Mask, Low A = AI Int Bit

S = RESET Bit (Resets DSP?)

CC005030  ?/W  16 bit    DMA Start address (High)

CC005032  ?/W  16 bit    DMA Start address (Low)

CC005036  ?/W  16 bit    DMA Control & DMA length     |SLLLL LLLL LLLL LLLL|  S = Status D = Length

                        Write (Length/4)&0x7FFF for Length. Set S to Play, Clear S to Stop

CC00503A  R/?  16 bit    DMA Bytes left

DI (DVD Interface) :

CC006000

SI (Serial Interface) :

CC006400

EXI (Expansion Interface) :

CC006800  ?/?  32 bit?   EXI Channel 0 Status

                        0x1000 – Something is inserted into Device 1

                        0x2000 – Something is inserted into Device 2

                        0x0800 – EXT Interrupt Occurred (Will trigger when device removed)

                        0x0400 – EXT Interrupt Mask

                        0x0380 – Device Select (0, 1, 2, 4, 5 seem valid)

                        0x0070 - Frequency

                        0x0008 – TC Interrupt Occurred

                        0x0004 – TC Interrupt Mask

                        0x0002 – EXI Interrupt Occurred

                        0x0001 – EXI Interrupt Mask (1-Enabled)

CC006804  ?/?  32 bit?   EXI Channel 0 DMA Start Address – Must be 32 byte aligned

CC006808  ?/?  32 bit?   EXI Channel 0 DMA Transfer Length

CC00680C  ?/?  32 bit?   EXI Channel 0 Control Register

                        0x0030 – EXI Data Size for Immediate (0 = Byte, 2 = Half-Word, 3 = Word)

                        0x000C – EXI Transfer Type (0 = Read, 1 = Write, 2..3???)

                        0x0002 – EXI Transfer Mode (0 = Immediate, 1 = DMA)

                        0x0001 – EXI Enable (Begins a Transfer)

CC006810  ?/?  32 bit?   EXI Channel 0 Immediate Data

CC006814  ?/?  32 bit?   EXI Channel 1 Status (Bits same as Channel 0)

CC006818  ?/?  32 bit?   EXI Channel 1 DMA Start Address

CC00681C  ?/?  32 bit?   EXI Channel 1 DMA Transfer Length

CC006820  ?/?  32 bit?   EXI Channel 1 Control Register (Bits same as Channel 0)

CC006824  ?/?  32 bit?   EXI Channel 1 Immediate Data

CC006828  ?/?  32 bit?   EXI Channel 2 Status (Bits same as Channel 0)

CC00682C  ?/?  32 bit?   EXI Channel 2 DMA Start Address

CC006830  ?/?  32 bit?   EXI Channel 2 DMA Transfer Length

CC006834  ?/?  32 bit?   EXI Channel 2 Control Register (Bits same as Channel 0)

CC006838  ?/?  32 bit?   EXI Channel 2 Immediate Data

Streaming Interface (Audio) :

CC006C00  ?/?  16 bit?   Audio Stream Status

                        Or with 0x40 for 32KHz and Clear 0x40 for 48Khz (Unconfirmed)

GX (Graphics Display Processor) :

CC008000  ?/W  32 bit    GX FIFO (Graphics Display Lists)

More to come…

Sources:

-         Titanik’s Crazy Nation Gamecube Source Pak #1; May 30, 2003, “gcninfos1.txt”

-         Audio demo by CrowTRobo; July 12, 2003, “ctr-snd.txt”

-         Various documents provided by org, author of Dolwin.

-         Costis of www.gcdev.com

-         F|RES of TR64 fame.

-    Various public documents

-         All other information obtained by Azimer through probing GC and emulating disc images on the PC.

*Sorry for not including your email addresses.  It prevents people from mass emailing all of you.*